The escalating requirements for high density and performance associated with ultra large scale integration technology creates significant challenges for the design and implementation of electrical connections between circuit components and external electrical circuitry.
Integrated circuit (IC) devices, whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active devices within a single chip, require suitable input/output (IO) connections between themselves and other circuit elements or structures. These devices are typically very small and fragile. Because of their size and fragility, they are commonly carried on substrates for support, i.e., carrier members.
One technique that supports the supports the increased device densities is the shift from peripheral wire bonding to area array chip interconnects. Area array chip interconnects involves bumps or solder joints that directly couple the IC chip or die to the carrier member. This technique accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed. One type of area array interconnect packaging technique is the flip chip (FC) solder interconnect on a carrier member.
In a flip chip assembly or package, the IC die and other devices are “bumped” with solder bumps or balls, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the die. The chip is then turned upside down or “flipped” so that the device side or face of the IC die couples to the carrier member such as found in a ceramic or plastic carrier member having balls, pins or land grid arrays. The solder bumps of the device are then attached to the carrier member through a eutectic solder reflow process to form an electrical and mechanical connection.
The carrier member conventionally employs a multi-layer substrate constructed of a plurality of laminated dielectric and conductive layers where individual IC chips are mounted to the top layer of the substrate. A pre-defined metallization pattern lies on each dielectric layer within the substrate. Metallization patterns on certain layers act as voltage reference planes and also provide power to the individual chips. Metallization patterns on other layers route signals between individual chips. Electrical connections to individual terminals of each chip and/or between separate layers are made through well-known vertical interconnects called “vias”. Interconnect pins are bonded to metallic pads situated on the face of the substrate and are thereby connected through appropriate metallization patterns existing within the substrate. These interconnect patterns route electrical signals between a multi-chip integrated circuit package and external devices.
Advances in microelectronics technology tend to develop chips that occupy less physical space while performing more electronic functions. Conventionally, each chip is packaged for use in housings that protect the chip from its environment and provide I/O communication between the chip and external circuitry through sockets or solder connections to a circuit board or the like. Miniaturization results in generating more heat in less physical space, with less structure for transferring heat from the package. The heat of concern is derived from wiring resistance and active components switching. The temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off.
As the chip and the substrate ordinarily are formed from different materials having different coefficiencies of thermal expansion (CTE), the chip and the substrate tend to expand and contract by different amounts, a phenomenon known as CTE mismatch. This causes the electrical contacts on the chip to move relative to electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and printed wiring board (PWB) and places them under mechanical stress. The stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections. This is especially true for the solder balls of controlled collapse chip connections, also known as “C4”, connections. It is therefore important to mitigate the substantial stress caused by thermal cycling as temperatures through the device change during operation.
Controlled collapse chip connection and flip chip technology has been successfully used for interconnecting high I/O count and area array solder bumps on the silicon chips to the base ceramic chip carriers (e.g., alumina carriers). In the C4 process, the solder wettable terminals on the chip are surrounded by ball limiting metallurgy and the matching footprint of solder wettable terminals on the corridors surrounded by a solder mass. These structures act to limit the flow of molten solder during reflow.
A eutectic reflow profile that has been employed to form the eutectic solder joints employs a 215° C. peak temperature, a cooling rate of 30° C./minutes and 2.7 minutes of hold time above the eutectic solder melting point of 183° C. It has been determined by the inventors that the solder microstructure in such joints is not equally distributed and dispersed throughout the eutectic solder joint. The relatively unequal distribution and dispersion of the solder microstructure resulting from the flip chip reflow process creates Sn boundaries which allow crack propagation along these grain boundaries to occur with repeated thermal cyclings.
For example, FIG. 1 depicts a cross-section of a solder joint 10 formed with a eutectic reflow profile as described above. A cross-section of the eutectic solder joint 10 reveals a solder bump 12 connected to under ball metallurgy 14 of a die 16.
The solder bump 12 has a high lead content, and is 95-97% lead (Pb) and approximately 3-5% tin (Sn). The eutectic solder 18 typically has a 63 Sn-37 Pb composition, with a melting temperature of 183° C., compared to the 320° C. melting temperature of the 95-97% Pb solder. After reflow, the eutectic solder 18 couples the solder bump and therefore the die 16, to the pad 20 of a package 22. A solder mask 24 defines a pad opening 26 above the pad. It is through this pad opening 26 that the eutectic solder 18 connects the pad 20 to the solder bump 12.
As can be appreciated from FIG. 1, the Sn 28 is not evenly dispersed and equally distributed within the eutectic solder joint 18 after the flip chip reflow. This creates grain boundaries 30 that allow solder cracking and causes open failures after repeated thermal cyclings.